A 3D package contains two or more integrated circuits stacked vertically so that they occupy less space. Many 3D packages use an integrated circuit-carrying substrate with through-silicon vias (TSVs). By using TSV technology instead of conventional edge wiring, 3D packages can pack a great deal of functionality into a small footprint. In addition, critical paths through the device can be effectively shortened, leading to reduced delay and faster operation.
TSV technology generally includes forming a through-substrate via, filling it to obtain a nail and bonding the nail to an interconnection structure on another wafer/chip, to realize a 3D package. Specifically, the following schemes may be employed: via-first, in which the TSV is made before making of the circuits; via-middle, in which the TSV is made after front-end-of-line processing (making of the devices) and before back-end-of-line processing (making of the interconnection structures); via-last, in which the TSV is made after making of the circuits, i.e. after making of the devices and the interconnection structures; and via-after-bonding, in which the TSV is made after bonding between two wafers or a chip to a wafer.
Conventional methods for forming a TSV are based on copper metallization techniques. FIG. 1 to FIG. 5 illustrate a cross-sectional view of an intermediate structure according to a conventional method for forming a TSV.
As shown in FIG. 1, a semiconductor substrate 10 is provided. The semiconductor substrate 10 may be provided with a semiconductor device (e.g., MOS transistor) or a semiconductor and an interconnection structure formed on it, or may be provided with no semiconductor devices or interconnection structures.
As shown in FIG. 2, the upper surface of the semiconductor substrate 10 is etched, to form an opening 11.
As shown in FIG. 3, a barrier layer 12 is formed over the bottom and sidewalls of the opening and the upper surface of the semiconductor substrate 10; then, metal copper 13 is formed on the barrier layer 12 by electroplating, which fills the opening. The method further includes forming a seed layer on the surface of the barrier layer 12 before forming the metal copper 13.
As shown in FIG. 4, the metal copper and the barrier layer 12 over the semiconductor substrate 10 are planarized such that the upper surface of the semiconductor substrate 10 is exposed, to form a nail 13a. 
As shown in FIG. 5, the semiconductor substrate 10 is thinned from its lower surface such that the nail 13a is exposed and the opening becomes a via passing completely through the semiconductor substrate 10, thereby finishing forming of the TSV.
No matter which scheme (via-first, via-middle, via-last or via-after-bonding) is employed, forming of TSVs based on copper metallization faces a big challenge in copper filling. For example, in applications such as MEMS (Microelectromechanical system), where a sensor is connected to a control circuit, the sensor and the control circuit can be made on respective semiconductor substrates, and TSVs can be used to connect each of the subunits of the sensor to a corresponding subunit of the control circuit, thereby simplifying design and production procedures and improving yield.
However, such applications require a high density of the TSVs, i.e., more TSVs per unit area. To meet the density requirement, the diameter of a TSV has to be kept small; meanwhile, the thickness of the semiconductor substrate should be large enough to maintain its mechanical strength, resulting in an aggressive aspect ratio of the TSV. As the aspect ratio of the TSV increases, especially when it is over 10:1, it will be difficult to form continuous barrier and seed layers. And the discontinuity of the barrier and seed layers may induce voids in the nail formed through electroplating, and cause reliability issues or even circuit breakage.
For more information on TSV technology, please refer to U.S. Pat. Nos. 7,683,459 and 7,633,165.